Copper metal has historically been used for ornamental uses in buildings. Recently, even for such ornamental copper products, to minimize the copper consumption, glossy copper plated on a resin article or the like has been often employed. In addition, copper is a good electric conductor and is not so expensive and easy to handle. Therefore, application of copper as a forming material in electric circuits has been expanding in recent generation. In the electronic circuit industry, surface mounting of electronic devices has been popular. Especially, as mounting of the devices on via holes are performed, to form filled via holes, copper plating is mainly employed. Further, for package substrates on which an IC chips are directly mounted, the pads for wire bonding may also be formed by copper plating. In such partially-plated copper plating, to minimize amount of plated gold on the surface and to improve connection reliability, the surface of plated copper film obtained by electro-deposition is required to be smooth and gloss.
Various technical developments have been carried out to satisfy such requirements described above. For example, Patent Document 1 discloses a technology in which a CV method is used to confirm whether a good electro-deposited film is obtained by using the bis(3-sulfopropyl)disulfideas an additive in a sulfuric acid base copper electrolytic solution for via filling. Next, Patent Document 2 discloses a technology managing a concentration of the oxygen in an electrolytic solution comprising a disulfide brightener to prevent the generation of a mono-sulfide which is generated by reductive decomposition in an electrolysis operation and adversely affect the plated film.
As can be understood from the technologies disclosed in Patent Documents 1 and 2, it is well known to use an active sulfur compound sulfonate as a brightener in a sulfuric acid base copper electrolytic solution.
[Patent Document 1] Japanese Patent Laid-Open No. 2005-171347
[Patent Document 2] Japanese Patent Laid-Open No. 2006-111976